Clock signals are used in virtually every IC and electronic system to control timing. For example, every time there is a rising edge on a clock signal, all the edge-triggered circuits, such as flip-flops, latches, and so on in an IC may change state. Frequently, both edges, rising and falling, of a clock signal are used in an IC and an electronic system. For example, in a two-phase logic, data is read into a first edge-triggered circuit on one edge of the clock signal, for example, during a falling edge, and a logic function is performed on the read data during the low phase. The data then appears at a second edge-triggered circuit and is outputted on the other edge of the clock signal, for example, during a rising edge, and another logic function is performed on the outputted data during a high phase. The data then appears at a third edge-triggered circuit and is outputted on the next edge of the clock cycle, for example, during a falling edge. Such functions are sometimes referred to as a combinational logic, where the logic functions in an IC are performed during both low and high phases of a clock cycle. Such edge-triggered circuits are generally edge sensitive.
The clock generator in an electronic system initially determines duty cycle of a clock signal. The duty cycle refers to a percentage of time a clock signal is “high” versus “low”. Clock generators are typically set to generate clock signals having a 50% duty cycle. As logic signals propagate through an Integrated circuit (IC), they can become distorted and a combinational logic function, such as the one described-above, can require a longer or shorter state than the initially set 50% duty cycle, to evaluate its function in a clock cycle. The distortion can result in uncertainty and a delay in logic signals which can result in a logic function requiring a longer or shorter percentage of time a clock signal to stay high or low during a clock cycle to improve system performance.
For the reasons stated above, and for reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for independently adjusting the duty cycle of a clock signal in an IC to compensate for any resulting uncertainty in the delay of the logic signals while propagating through an IC to improve system performance.